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ddr2 sdram vlp rdimm mt36hvs25672py C 2gb mt36hvs51272py C 4gb mt36hvzs51272py C 4gb features ? 240-pin, registered very low profile, dual in-line memory module, atca form factor ? fast data transfer rates: pc2-4200, pc2-5300, or pc2-6400 ? 2gb (256 meg x 72) or 4gb (512 meg x 72) ? supports ecc error detection and correction ? v dd = v ddq = 1.8v ? v ddspd = 1.7C3.6v ? jedec-standard 1.8v i/o (sstl_18-compatible) ? differential data strobe (dqs, dqs#) option ? 4 n -bit prefetch architecture ? dual rank using twindie ? devices ? multiple internal device banks for concurrent operation ? programmable cas latency (cl) ? posted cas additive latency (al) ? write latency = read latency - 1 t ck ? programmable burst lengths (bl): 4 or 8 ? adjustable data-output drive strength ? 64ms, 8192-cycle refresh ? on-die termination (odt) ? serial presence-detect (spd) with eeprom ? gold edge contacts figure 1: 240-pin rdimm (atca form factor) module height: 17.9mm (0.705in) options marking ? full module heat spreader 1 z ? parity p ? operating temperature C commercial (0c t a +70c) none C industrial (C40c t a +85c) 2 i ? package C 240-pin dimm (lead-free) y ? frequency/cl 3 C 2.5ns @ cl = 5 (ddr2-800) -80e C 2.5ns @ cl = 6 (ddr2-800) -800 C 3.0ns @ cl = 6 (ddr2-667) -667 C 3.75ns @ cl = 5 (ddr2-533) 4 -53e notes: 1. 4gb density only. 2. contact micron for industrial temperature module offerings. 3. cl = cas (read) latency; registered mode will add one clock cycle to cl. 4. not recommended for new designs. table 1: key timing parameters speed grade industry nomenclature data rate (mt/s) t rcd (ns) t rp (ns) t rc (ns) cl = 6 cl = 5 cl = 4 cl = 3 -80e pc2-6400 800 800 533 400 12.5 12.5 55 -800 pc2-6400 800 667 533 400 15 15 55 -667 pc2-5300 C 667 553 400 15 15 55 -53e pc2-4200 C C 553 400 15 15 55 -40e pc2-3200 C C 400 400 15 15 55 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm features pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
table 2: addressing parameter 2gb 4gb refresh count 8k 8k row address 16k a[13:0] 16k a[13:0] device bank address 4 ba[2:0] 8 ba[2:0] device configuration 1gb twindie (256 meg x 4) 2gb twindie (512 meg x 4) column address 2k a[9:0] 2k a[9:0] module rank address 2 s#[1:0] 2 s#[1:0] table 3: part numbers and timing parameters C 2gb base device: mt47h256m4thk, 1 1gb twindie ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt36hvs25672p(i)y-667__ 2gb 256 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt36hvs25672p(i)y-53e__ 2gb 256 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 table 4: part numbers and timing parameters C 4gb base device: mt47h512m4thn, 1 2gb twindie ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt36hvs51272p(i)y-80e__ 4gb 512 meg x 72 6.2 gb/s 2.5ns/800 mt/s 5-5-5 mt36hvs51272p(i)y-800__ 4gb 512 meg x 72 6.2 gb/s 2.5ns/800 mt/s 6-6-6 mt36hvs51272p(i)y-667__ 4gb 512 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt36hvs51272p(i)y-53e__ 4gb 512 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 table 5: part numbers and timing parameters C 4gb base device: mt47h512m4thn, 1 2gb twindie ddr2 sdram part number 2 module density configuration module bandwidth memory clock/ data rate clock cycles (cl- t rcd- t rp) mt36hvzs51272p(i)y-80e__ 4gb 512 meg x 72 6.2 gb/s 2.5ns/800 mt/s 5-5-5 mt36hvzs51272p(i)y-800__ 4gb 512 meg x 72 6.2 gb/s 2.5ns/800 mt/s 6-6-6 mt36hvzs51272p(i)y-667__ 4gb 512 meg x 72 5.3 gb/s 3.0ns/667 mt/s 5-5-5 mt36hvzs51272p(i)y-53e__ 4gb 512 meg x 72 4.3 gb/s 3.75ns/533 mt/s 4-4-4 notes: 1. data sheets for the base device can be found on microns web site. 2. all part numbers end with a two-place code (not shown) that designates component and pcb revisions. con- sult factory for current revision codes. example: mt36hvs51272py-667 d1. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm features pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
pin assignments table 6: pin assignments 240-pin vlp rdimm front 240-pin vlp rdimm back pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol pin symbol 1 v ref 31 dq19 61 a4 91 v ss 121 v ss 151 v ss 181 v ddq 211 dqs14 2 v ss 32 v ss 62 v ddq 92 dqs5# 122 dq4 152 dq28 182 a3 212 dqs14# 3 dq0 33 dq24 63 a2 93 dqs5 123 dq5 153 dq29 183 a1 213 v ss 4 dq1 34 dq25 64 v dd 94 v ss 124 v ss 154 v ss 184 v dd 214 dq46 5 v ss 35 v ss 65 v ss 95 dq42 125 dqs9 155 dqs12 185 ck0 215 dq47 6 dqs0# 36 dqs3# 66 v ss 96 dq43 126 dqs9# 156 dqs12# 186 ck0# 216 v ss 7 dqs0 37 dqs3 67 v dd 97 v ss 127 v ss 157 v ss 187 v dd 217 dq52 8 v ss 38 v ss 68 par_in 98 dq48 128 dq6 158 dq30 188 a0 218 dq53 9 dq2 39 dq26 69 v dd 99 dq49 129 dq7 159 dq31 189 v dd 219 v ss 10 dq3 40 dq27 70 a10 100 v ss 130 v ss 160 v ss 190 ba1 220 nc 11 v ss 41 v ss 71 ba0 101 sa2 131 dq12 161 cb4 191 v ddq 221 nc 12 dq8 42 cb0 72 v ddq 102 nc 132 dq13 162 cb5 192 ras# 222 v ss 13 dq9 43 cb1 73 we# 103 v ss 133 v ss 163 v ss 193 s0# 223 dqs15 14 v ss 44 v ss 74 cas# 104 dqs6# 134 dqs10 164 dqs17 194 v ddq 224 dqs15# 15 dqs1# 45 dqs8# 75 v ddq 105 dqs6 135 dqs10# 165 dqs17# 195 odt0 225 v ss 16 dqs1 46 dqs8 76 s1# 106 v ss 136 v ss 166 v ss 196 a13 226 dq54 17 v ss 47 v ss 77 odt1 107 dq50 137 rfu 167 cb6 197 v dd 227 dq55 18 reset# 48 cb2 78 v ddq 108 dq51 138 rfu 168 cb7 198 v ss 228 v ss 19 nc 49 cb3 79 v ss 109 v ss 139 v ss 169 v ss 199 dq36 229 dq60 20 v ss 50 v ss 80 dq32 110 dq56 140 dq14 170 v ddq 200 dq37 230 dq61 21 dq10 51 v ddq 81 dq33 111 dq57 141 dq15 171 cke1 201 v ss 231 v ss 22 dq11 52 cke0 82 v ss 112 v ss 142 v ss 172 v dd 202 dqs13 232 dqs16 23 v ss 53 v dd 83 dqs4# 113 dqs7# 143 dq20 173 a15 203 dqs13# 233 dqs16# 24 dq16 54 nc/ba2 1 84 dqs4 114 dqs7 144 dq21 174 a14 204 v ss 234 v ss 25 dq17 55 err_out# 85 v ss 115 v ss 145 v ss 175 v ddq 205 dq38 235 dq62 26 v ss 56 v ddq 86 dq34 116 dq58 146 dqs11 176 a12 206 dq39 236 dq63 27 dqs2# 57 a11 87 dq35 117 dq59 147 dqs11# 177 a9 207 v ss 237 v ss 28 dqs2 58 a7 88 v ss 118 v ss 148 v ss 178 v dd 208 dq44 238 v ddspd 29 v ss 59 v dd 89 dq40 119 sda 149 dq22 179 a8 209 dq45 239 sa0 30 dq18 60 a5 90 dq41 120 scl 150 dq23 180 a6 210 v ss 240 sa1 note: 1. pin 54 is nc for 2gb and ba2 for 4gb. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm pin assignments pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
pin descriptions the pin description table below is a comprehensive list of all possible pins for all ddr2 modules. all pins listed may not be supported on this module. see pin assignments for information specific to this module. table 7: pin descriptions symbol type description ax input address inputs: provide the row address for active commands, and the column ad- dress and auto precharge bit (a10) for read/write commands, to select one location out of the memory array in the respective bank. a10 sampled during a precharge command determines whether the precharge applies to one bank (a10 low, bank selected by bax) or all banks (a10 high). the address inputs also provide the op-code during a load mode command. see the pin assignments table for density-specific addressing information. bax input bank address inputs: define the device bank to which an active, read, write, or precharge command is being applied. ba define which mode register (mr0, mr1, mr2, and mr3) is loaded during the load mode command. ckx, ck#x input clock: differential clock inputs. all control, command, and address input signals are sampled on the crossing of the positive edge of ck and the negative edge of ck#. ckex input clock enable: enables (registered high) and disables (registered low) internal circui- try and clocks on the ddr2 sdram. dmx, input data mask (x8 devices only): dm is an input mask signal for write data. input data is masked when dm is sampled high, along with that input data, during a write ac- cess. although dm pins are input-only, dm loading is designed to match that of the dq and dqs pins. odtx input on-die termination: enables (registered high) and disables (registered low) termi- nation resistance internal to the ddr2 sdram. when enabled in normal operation, odt is only applied to the following pins: dq, dqs, dqs#, dm, and cb. the odt input will be ignored if disabled via the load mode command. par_in input parity input: parity bit for ax, ras#, cas#, and we#. ras#, cas#, we# input command inputs: ras#, cas#, and we# (along with s#) define the command being entered. reset# input reset: asynchronously forces all registered outputs low when reset# is low. this signal can be used during power-up to ensure that cke is low and dq are high-z. s#x input chip select: enables (registered low) and disables (registered high) the command decoder. sax input serial address inputs: used to configure the spd eeprom address range on the i 2 c bus. scl input serial clock for spd eeprom: used to synchronize communication to and from the spd eeprom on the i 2 c bus. cbx i/o check bits. used for system error detection and correction. dqx i/o data input/output: bidirectional data bus. dqsx, dqs#x i/o data strobe: travels with the dq and is used to capture dq at the dram or the con- troller. output with read data; input with write data for source synchronous opera- tion. dqs# is only used when differential data strobe mode is enabled via the load mode command. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm pin descriptions pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 7: pin descriptions (continued) symbol type description sda i/o serial data: used to transfer addresses and data into and out of the spd eeprom on the i 2 c bus. rdqsx, rdqs#x output redundant data strobe (x8 devices only): rdqs is enabled/disabled via the load mode command to the extended mode register (emr). when rdqs is enabled, rdqs is output with read data only and is ignored during write data. when rdqs is disa- bled, rdqs becomes data mask (see dmx). rdqs# is only used when rdqs is enabled and differential data strobe mode is enabled. err_out# output (open drain) parity error output: parity error found on the command and address bus. v dd /v ddq supply power supply: 1.8v 0.1v. the component v dd and v ddq are connected to the mod- ule v dd . v ddspd supply spd eeprom power supply: 1.7C3.6v. v ref supply reference voltage: v dd /2. v ss supply ground. nc C no connect: these pins are not connected on the module. nf C no function: these pins are connected within the module, but provide no functionality. nu C not used: these pins are not used in specific module configurations/operations. rfu C reserved for future use. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm pin descriptions pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
functional block diagram figure 2: functional block diagram dm cs# dqs dqs# dq dq dq dq dq0 dq1 dq2 dq3 dq dq dq dq u1b u1t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq4 dq5 dq6 dq7 dq dq dq dq u22b u22t dm cs# dqs dqs# dqs0 dqs0# dqs9 dqs9# dm cs# dqs dqs# dq dq dq dq dq8 dq9 dq10 dq11 dq dq dq dq u2b u2t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq12 dq13 dq14 dq15 dq dq dq dq u21b u21t dm cs# dqs dqs# dqs1 dqs1# dqs10 dqs10# dm cs# dqs dqs# dq dq dq dq dq16 dq17 dq18 dq19 dq dq dq dq u3b u3t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq20 dq21 dq22 dq23 dq dq dq dq u20b u20t dm cs# dqs dqs# dqs2 dqs2# dqs11 dqs11# dm cs# dqs dqs# dq dq dq dq dq24 dq25 dq26 dq27 dq dq dq dq u4b u4t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq28 dq29 dq30 dq31 dq dq dq dq u19b u19t dm cs# dqs dqs# dqs3 dqs3# dqs12 dqs12# dm cs# dqs dqs# dq dq dq dq dq dq dq dq dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq dq dq dq dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq32 dq33 dq34 dq35 dq dq dq dq u9b u9t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq36 dq37 dq38 dq39 dq dq dq dq u15b u15t dm cs# dqs dqs# dqs4 dqs4# dqs13 dqs13# dm cs# dqs dqs# dq dq dq dq dq40 dq41 dq42 dq43 dq dq dq dq u10b u10t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq44 dq45 dq46 dq47 dq dq dq dq u14b u14t dm cs# dqs dqs# dqs5 dqs5# dqs14 dqs14# dm cs# dqs dqs# dq dq dq dq dq48 dq49 dq50 dq51 dq dq dq dq u11b u11t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq52 dq53 dq54 dq55 dq dq dq dq u13b u13t dm cs# dqs dqs# dqs6 dqs6# dqs15 dqs15# dm cs# dqs dqs# dq dq dq dq dq56 dq57 dq58 dq59 dq dq dq dq u8b u8t dm cs# dqs dqs# dm cs# dqs dqs# dq dq dq dq dq60 dq61 dq62 dq63 dq dq dq dq u16b u16t dm cs# dqs dqs# dqs7 dqs7# dqs16 dqs16# a0 spd eeprom a1 a2 sa0 sa1 sa2 sda scl wp r e g i s t e r s pll s0# s1# ba[2:0] a[15:0] ras# cas# we# cke0 cke1 odt0 odt1 par_in reset# rs0#: rank 0 rs1#: rank 1 rba[2:0]: ddr2 sdram ra[13:0]: ddr2 sdram rras#: ddr2 sdram rcas#: ddr2 sdram rwe#: ddr2 sdram rcke0: rank 0 rcke1: rank 1 rodt0: rank 0 rodt1: rank 1 err_out# ck0 ck0# ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 ddr2 sdram x 4 register x 2 reset# u6 v ss ddr2 sdram ddr2 sdram v dd /v ddq spd eeprom ddr2 sdram u7, u17 u12 v ss rs0# rs1# cb0 cb1 cb2 cb3 u5b u5t cb4 cb5 cb6 cb7 u18b dqs8 dqs8# dqs17 dqs17# u18t rank 0 = u1bCu5b, u8bCu11b, u13bCu16b, u18bCu22b rank 1 = u1tCu5t, u8tCu11t, u13tCu16t, u18tCu22t v ss v ddspd v ref 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm functional block diagram pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
general description ddr2 sdram modules are high-speed, cmos dynamic random access memory mod- ules that use internally configured 4 or 8-bank ddr2 sdram devices. ddr2 sdram modules use ddr architecture to achieve high-speed operation. ddr2 architecture is essentially a 4 n -prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o pins. a single read or write access for the ddr2 sdram module effectively consists of a single 4 n -bit-wide, one-clock-cycle data transfer at the internal dram core and eight corresponding n -bit-wide, one-half-clock-cycle data trans- fers at the i/o pins. ddr2 modules use two sets of differential signals: dqs, dqs# to capture data and ck and ck# to capture commands, addresses, and control signals. differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. a bidirectional data strobe (dqs, dqs#) is trans- mitted externally, along with data, for use in data capture at the receiver. dqs is a strobe transmitted by the ddr2 sdram device during reads and by the memory con- troller during writes. dqs is edge-aligned with data for reads and center-aligned with data for writes. ddr2 sdram modules operate from a differential clock (ck and ck#); the crossing of ck going high and ck# going low will be referred to as the positive edge of ck. com- mands (address and control signals) are registered at every positive edge of ck. input data is registered on both edges of dqs, and output data is referenced to both edges of dqs, as well as to both edges of ck. serial presence-detect eeprom operation ddr2 sdram modules incorporate serial presence-detect. the spd data is stored in a 256-byte eeprom. the first 128 bytes are programmed by micron to identify the mod- ule type and various sdram organizations and timing parameters. the remaining 128 bytes of storage are available for use by the customer. system read/write operations between the master (system logic) and the slave eeprom device occur via a standard i 2 c bus using the dimms scl (clock) sda (data), and sa (address) pins. write protect (wp) is connected to v ss , permanently disabling hardware write protection. register and pll operation ddr2 sdram modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the ddr2 sdram devices on the following rising clock edge (data access is delayed by one clock cycle). a phase-lock loop (pll) on the module receives and redrives the differential clock signals (ck, ck#) to the ddr2 sdram devices. the registers and pll minimize system and clock loading. pll clock timing is defined by jedec specifications and en- sured by use of the jedec clock reference board. registered mode will add one clock cycle to cl. parity operations the registering clock driver can accept a parity bit from the systems memory control- ler, providing even parity for the control, command, and address bus. parity errors are flagged on the err_out# pin. systems not using parity are expected to function without issue if par_in and err_out# are left as no connects (nc) to the system. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm general description pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
electrical specifications stresses greater than those listed may cause permanent damage to the module. this is a stress rating only, and functional operation of the module at these or any other condi- tions outside those indicated in each device's data sheet is not implied. exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. table 8: absolute maximum ratings symbol parameter min max units v dd /v ddq v dd /v ddq supply voltage relative to v ss C0.5 2.3 v v in , v out voltage on any pin relative to v ss C0.5 2.3 v i i input leakage current; any input 0v v in v dd ; v ref input 0v v in 0.95v; (all other pins not under test = 0v) command/address, ras#, cas#, we# s#, cke, odt, ba C10 10 a ck, ck# C250 250 i oz output leakage current; 0v v out v ddq ; dqs and odt are disabled dq, dqs, dqs# C10 10 a i vref v ref leakage current; v ref = valid v ref level C72 72 a t a module ambient operating temperature commercial 0 70 c industrial C40 85 t c 1 ddr2 sdram device operating case temper- ature 2 commercial 0 85 c industrial C40 95 notes: 1. the refresh rate is required to double when t c exceeds 85c. 2. for further information, refer to technical note tn-00-08: "thermal applications," avail- able on microns web site. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm electrical specifications pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
dram operating conditions recommended ac operating conditions are given in the ddr2 component data sheets. component specifications are available on micron's web site. module speed grades cor- relate with component speed grades. table 9: module and component speed grades ddr2 components may exceed the listed module speed grades; module may not be available in all listed speed grades module speed grade component speed grade -1ga -187e -80e -25e -800 -25 -667 -3 -53e -37e -40e -5e design considerations simulations micron memory modules are designed to optimize signal integrity through carefully de- signed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. however, good signal integrity starts at the system level. mi- cron encourages designers to simulate the signal characteristics of the system's memo- ry bus to ensure adequate signal integrity of the entire memory system. power operating voltages are specified at the dram, not at the edge connector of the module. designers must account for any system voltage drops at anticipated power levels to en- sure the required supply voltage is maintained. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm dram operating conditions pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
i dd specifications table 10: ddr2 i dd specifications and conditions C 2gb values shown for mt47h256m4 ddr2 sdram only and are computed from values specified in the 1gb twindie (256 meg x 4) component data sheet parameter combined symbol -667 -53e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd0 1 1836 1656 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i cdd1 1 2106 1926 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus inputs are floating i cdd2p 2 252 252 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i dd2q 2 1026 936 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i cdd2n 2 1116 1026 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus inputs are sta- ble; data bus inputs are floating fast pdn exit mr[12] = 0 i cdd3p 2 756 666 ma slow pdn exit mr[12] = 1 342 342 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; other con- trol and address bus inputs are switching; data bus inputs are switching i cdd3n 2 1386 1206 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switch- ing; data bus inputs are switching i dd4w 1 3276 2736 ma operating burst read current: all device banks open; continuous burst read, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd4r 1 3456 2826 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) inter- val; cke is high, s# is high between valid commands; other control and address bus inputs are switching; data bus inputs are switching i cdd5 2 3456 3276 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i cdd6 2 252 252 ma 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm i dd specifications pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 10: ddr2 i dd specifications and conditions C 2gb (continued) values shown for mt47h256m4 ddr2 sdram only and are computed from values specified in the 1gb twindie (256 meg x 4) component data sheet parameter combined symbol -667 -53e units operating bank interleave read current: all device banks interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i cdd7 1 4536 4266 ma notes: 1. value calculated as one module rank in this operating condition. all other module ranks in i dd2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm i dd specifications pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 11: ddr2 i dd specifications and conditions C 4gb values shown for mt47h128m8 ddr2 sdram only and are computed from values specified in the 2gb twindie (512 meg x 4) component data sheet parameter combined symbol -80e/ -800 -667 -53e units operating one bank active-precharge current: t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ); cke is high, s# is high between valid com- mands; address bus inputs are switching; data bus inputs are switching i cdd0 1 1836 1746 1476 ma operating one bank active-read-precharge current: i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t rc = t rc (i dd ), t ras = t ras min (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data pattern is same as i dd4w i cdd1 1 2196 2016 1926 ma precharge power-down current: all device banks idle; t ck = t ck (i dd ); cke is low; other control and address bus inputs are stable; data bus in- puts are floating i cdd2p 2 252 252 252 ma precharge quiet standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are stable; data bus inputs are floating i cdd2q 2 1026 846 846 ma precharge standby current: all device banks idle; t ck = t ck (i dd ); cke is high, s# is high; other control and address bus inputs are switching; data bus inputs are switching i cdd2n 2 1116 936 936 ma active power-down current: all device banks open; t ck = t ck (i dd ); cke is low; other control and address bus in- puts are stable; data bus inputs are floating fast pdn exit mr[12] = 0 i cdd3p 2 846 666 666 ma slow pdn exit mr[12] = 1 306 306 306 active standby current: all device banks open; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid com- mands; other control and address bus inputs are switching; data bus in- puts are switching i cdd3n 2 1296 1206 1026 ma operating burst write current: all device banks open; continuous burst writes; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid commands; address bus inputs are switching; data bus inputs are switching i cdd4w 1 2826 2376 2196 ma operating burst read current: all device banks open; continuous burst read, i out = 0ma; bl = 4, cl = cl (i dd ), al = 0; t ck = t ck (i dd ), t ras = t ras max (i dd ), t rp = t rp (i dd ); cke is high, s# is high between valid com- mands; address bus inputs are switching; data bus inputs are switching i dd4r 1 2826 2376 2196 ma burst refresh current: t ck = t ck (i dd ); refresh command at every t rfc (i dd ) interval; cke is high, s# is high between valid commands; other con- trol and address bus inputs are switching; data bus inputs are switching i cdd5 2 4446 4086 3996 ma self refresh current: ck and ck# at 0v; cke 0.2v; other control and address bus inputs are floating; data bus inputs are floating i cdd6 2 252 252 252 ma 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm i dd specifications pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 11: ddr2 i dd specifications and conditions C 4gb (continued) values shown for mt47h128m8 ddr2 sdram only and are computed from values specified in the 2gb twindie (512 meg x 4) component data sheet parameter combined symbol -80e/ -800 -667 -53e units operating bank interleave read current: all device banks interleaving reads, i out = 0ma; bl = 4, cl = cl (i dd ), al = t rcd (i dd ) - 1 t ck (i dd ); t ck = t ck (i dd ), t rc = t rc (i dd ), t rrd = t rrd (i dd ), t rcd = t rcd (i dd ); cke is high, s# is high between valid commands; address bus inputs are stable during deselects; data bus inputs are switching i cdd7 1 6246 5256 5076 ma notes: 1. value calculated as one module rank in this operating condition. all other module ranks in i dd2p (cke low) mode. 2. value calculated reflects all module ranks in this operating condition. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm i dd specifications pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
register and pll specifications table 12: register specifications sstu32866 devices or equivalent parameter symbol pins condition min max units dc high-level input voltage v ih(dc) control, command, address sstl_18 v ref(dc) + 125 v ddq + 250 mv dc low-level input voltage v il(dc) control, command, address sstl_18 0 v ref(dc) - 125 mv ac high-level input voltage v ih(ac) control, command, address sstl_18 v ref(dc) + 250 C mv ac low-level input voltage v il(ac) control, command, address sstl_18 C v ref(dc) - 250 mv output high voltage v oh parity output lvcmos 1.2 C v output low voltage v ol parity output lvcmos C 0.5 v input current i i all pins v i = v dd or v ss C 0.5 a static standby i dd all pins reset# = v ssq (i o = 0) C5 5 ma static operating i dd all pins reset# = v ss ; v i = v ih(ac) or v il(dc) i o = 0 C 100 ma dynamic operating (clock tree) i ddd n/a reset# = v dd ; v i = v ih(dc) or v il(ac) , i o = 0; ck and ck# switch- ing 50% duty cycle C varies by manufacturer a dynamic operating (per each input) i ddd n/a reset# = v dd ; v i = v ih(ac) or v il(dc) , i o = 0; ck and ck# switching 50% duty cy- cle; one data in/out switching at t ck/2, 50% duty cycle C varies by manufacturer a input capacitance (per device, per pin) c in all inputs except reset# v i = v ref 250mv; v dd = 1.8v 2.5 3.5 pf input capacitance (per device, per pin) c in reset# v i = v dd or v ss varies by manufacturer varies by manufacturer pf note: 1. timing and switching specifications for the register listed are critical for proper opera- tion of the ddr2 sdram rdimms. these are meant to be a subset of the parameters for the specific device used on the module. detailed information for this register is available in jedec standard jesd82. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm register and pll specifications pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
table 13: pll specifications cu877 device or equivalent parameter symbol pins condition min max units dc high-level input voltage v ih reset# lvcmos 0.65 v dd C v dc low-level input voltage v il reset# lvcmos C 0.35 v dd v input voltage (limits) v in reset#, ck, ck# C 0.3 v dd + 0.3 v dc high-level input voltage v ih ck, ck# differential input 0.65 v dd C v dc low-level input voltage v il ck, ck# differential input C 0.35 v dd v input differential-pair cross voltage v ix ck, ck# differential input (v ddq /2) - 0.15 (v dd /2) - 0.15 v input differential voltage v id(dc) ck, ck# differential input 0.3 v dd - 0.4 v input differential voltage v id(ac) ck, ck# differential input 0.6 v dd - 0.4 v input current i i reset# v i = v dd or v ss C10 10 a ck, ck# v i = v dd or v ss C250 250 a output disabled current i odl reset# = v ss ; v i = v ih(ac) or v il(dc) 100 C a static supply current i ddld ck = ck# = low C 500 a dynamic supply i dd n/a ck, ck# = 270 mhz, all outputs open (not con- nected to pcb) C 300 ma input capacitance c in each input v i = v dd or v ss 2 3 pf table 14: pll clock driver timing requirements and switching characteristics parameter symbol min max units stabilization time t l C 15 s input clock slew rate slr(i) 1.0 4.0 v/ns ssc modulation frequency C 30 33 khz ssc clock input frequency deviation C 0.0 C0.5 % pll loop bandwidth (C3db from unity gain) C 2.0 C mhz note: 1. pll timing and switching specifications are critical for proper operation of the ddr2 dimm. this is a subset of parameters for the specific pll used. detailed pll information is available in jedec standard jesd82. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm register and pll specifications pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
serial presence-detect for the latest spd data, refer to micron's spd page: www.micron.com/spd . table 15: spd eeprom operating conditions parameter/condition symbol min max units supply voltage v ddspd 1.7 3.6 v input high voltage: logic 1; all inputs v ih v ddspd 0.7 v ddspd + 0.5 v input low voltage: logic 0; all inputs v il C0.6 v ddspd 0.3 v output low voltage: i out = 3ma v ol C 0.4 v input leakage current: v in = gnd to v dd i li 0.1 3 a output leakage current: v out = gnd to v dd i lo 0.05 3 a standby current i sb 1.6 4 a power supply current, read: scl clock frequency = 100 khz i ccr 0.4 1 ma power supply current, write: scl clock frequency = 100 khz i ccw 2 3 ma table 16: spd eeprom ac operating conditions parameter/condition symbol min max units notes scl low to sda data-out valid t aa 0.2 0.9 s 1 time bus must be free before a new transition can start t buf 1.3 C s data-out hold time t dh 200 C ns sda and scl fall time t f C 300 ns 2 sda and scl rise time t r C 300 ns 2 data-in hold time t hd:dat 0 C s start condition hold time t hd:sta 0.6 C s clock high period t high 0.6 C s noise suppression time constant at scl, sda inputs t i C 50 s clock low period t low 1.3 C s scl clock frequency t scl C 400 khz data-in setup time t su:dat 100 C ns start condition setup time t su:sta 0.6 C s 3 stop condition setup time t su:sto 0.6 C s write cycle time t wrc C 10 ms 4 notes: 1. to avoid spurious start and stop conditions, a minimum delay is placed between scl = 1 and the falling or rising edge of sda. 2. this parameter is sampled. 3. for a restart condition or following a write cycle. 4. the spd eeprom write cycle time ( t wrc) is the time from a valid stop condition of a write sequence to the end of the eeprom internal erase/program cycle. during the write cycle, the eeprom bus interface circuit is disabled, sda remains high due to pull- up resistance, and the eeprom does not respond to its slave address. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm serial presence-detect pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.
module dimensions figure 3: 240-pin ddr2 vlp rdimm 18.05 (0.711) 17.75 (0.699) pin 1 2.5 (0.098) d (2x) 2.3 (0.091) typ 5 (0.25) typ 123 (4.84) typ 1.0 (0.039) typ 2.2 (0.087) typ 0.8 (0.04) typ 2.0 (0.079) r (4x) 0.75 (0.029) r pin 120 front view 133.50 (5.256) 133.20 (5.244) 63.0 (2.48) typ 55.0 (2.16) typ 10.0 (0.394) typ back view pin 240 pin 121 1.37 (0.054) 1.17 (0.046) 3.99 (0.157) max 1.0 (0.039) typ 3.05 (0.012) typ 70.68 (2.78) typ u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 u11 u12 u13 u14 u15 u16 u17 u18 u19 u20 u21 u22 1.37 (0.054) 1.17 (0.046) 9.1 (0.358) max with heat spreader attached notes: 1. all dimensions are in millimeters (inches); max/min or typical (typ) where noted. 2. the dimensional diagram is for reference only. 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 2gb, 4gb (x72, ecc, dr) 240-pin ddr2 sdram vlp rdimm module dimensions pdf: 09005aef83e49b25 hv-z-s36c256_512x72py.pdf - rev. d 03/10 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2006 micron technology, inc. all rights reserved.

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